PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe) industry-standard input/output (I/O) technology, announced the approval of 16 gigatransfers per second (GT/s) as the bit rate for the next generation of PCIe architecture, PCIe 4.0. This decision comes after the PCI-SIG completed a feasibility study on scaling the PCIe interconnect bandwidth to meet the demands of a variety of computing markets.
After technical analysis, the PCI-SIG has determined that 16 GT/s on copper, which will double the bandwidth over the PCIe 3.0 specification, is technically feasible at approximately PCIe 3.0 power levels. The data also confirms that a 16GT/s interconnect can be manufactured in mainstream silicon process technology and can be deployed with existing low-cost materials and infrastructure, while maintaining compatibility with previous generations of PCIe architecture. In addition, the PCI-SIG will investigate advancements in active and idle power optimizations, key issues facing the industry.
Approximately 24 billion lanes of PCIe have shipped in the marketplace since its introduction-a strong testament to the industry's reliance on PCIe architecture as an open bus standard now and for the future. This next-generation PCIe architecture, while doubling the data rate, will maintain its position as a low-cost, high-performance I/O technology. PCIe 4.0 technology will maintain backward compatibility with previous PCIe architectures and provide the optimum design point for high-volume platform I/O implementations across a wide range of existing and emerging applications. The PCIe 4.0 specification will address the many applications pushing for increased bandwidth at a low cost including server, workstation, desktop PC, notebook PC, tablets, embedded systems, peripheral devices, high-performance computing markets and more.
The final PCIe 4.0 specifications, including form factor specification updates, are expected to be available sometime in the 2014-2015 timeframe.
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